This invention relates to a current sense circuit for detecting read current from a memory cell in a ROM (Read-Only Memory) device such as a mask ROM (mask Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), and EEPROM (Electrically Erasable Programmable Read-Only Memory).
Read-only memory devices (hereinafter called ROMs) generally take much longer access time than other types of memory devices. To improve the access speed of ROMs by increasing the rate of signal propagation on the word lines, the inventor has proposed a ROM, described in Japanese Patent Application Laid-open 1986/123000, in which the bias of the memory elements is opposite to that employed previously, and a current sense circuit, described in Japanese Patent Application Laid-open 1986/129800, in which the current inflow from the selected data line is detected. The U.S. Pat. No. 4,709,352, which claims the Convention Priority from these two Japanese applications, discloses the above features.
FIG. 1 is a schematic diagram of the aforesaid current sense circuit. This current sense circuit comprises a pair of identical depletion-type MOS field-effect transistors (hereinafter referred to as MOS FETs) 1 and 2, a pair of identical enhancement-type MOS FETs 3 and 4, and a pair of identical enhancement-type MOS FETs 5 and 6. The MOS FETs 1, 3, and 5 are connected in series between the high supply voltage Vcc and the low supply voltage Vss, and their gates are connected in common to the source of the MOS FET 1. The MOS FETs 2, 4, and 6 are also connected in series between the high supply voltage Vcc and the low supply voltage Vss, and the gates of the MOS FETs 2 and 6 are connected in common to the source of the MOS FET 2. The gate of the MOS FET 4 is connected to the gate of the MOS FET 3.
A reference current Ir is supplied to a node N1 disposed between the source of the MOS FET 3 and the drain of the MOS FET 5. A read current I representing a bit of data to be read is supplied to a node N2 disposed between the source of the MOS FET 4 and the drain of the MOS FET 6. A node N3 disposed between the source of the MOS FET 1 and the drain of the MOS FET 3 and a node N4 disposed between the source of the MOS FET 2 and the drain of the MOS FET 4 are connected to two input terminals 8a and 8b of a differential amplifier 8 which provides the amplified difference of their potentials to an output circuit, not shown. The potentials at the nodes N3 and N4 are indicative of the current inputs I and Ir.
In the current sense circuit, the potentials at the nodes N1 and N2 are held to constant values determined by the circuit parameters and the reference current Ir, so it can quickly correct potential fluctuations due to switching from one bit to another, permitting high-speed read access. In other words, the above-described current sense circuit should be distinguished from a voltage sense circuit which detects the voltage variation on the data line which varies depending on the read data bit. Rather, the above-described current sense circuit maintains the potential of the data line and instead detects the current through the data line which varies depending on the read data bit. This scheme is advantageous because it permits high-speed reading.
One of the requisite conditions for the above described circuit to operate successfully is that the value of the reference current Ir must be substantially midway between the two values of the read current I. When the read data bit is "0", the read current is a smaller value I.sub.S which is about 0 to 20.mu.A. When the read data bit is "1", the read current is a larger value I.sub.L which is about 50 to 70.mu.A. The reference current Ir must therefore be set about 35.mu.A. It is difficult to provide this small current with a high reliability and a good stability. In this connection, it must be noted that the actual value of the read current I (=I.sub.L or I.sub.S) varies in a nonlinear fashion with fluctuations in the supply voltage Vcc. ROMs using this current sense circuit therefore have a small noise margin; fluctuations in the power supply tend to cause read-out errors.